1. Technical Field
The present invention relates generally to an improved data processing system. In particular, the present invention relates to a method, apparatus, and computer instructions for providing valid translation entries in the translation control entry (TCE) table for all supported direct memory access (DMA) addresses.
2. Description of Related Art
Current peripheral component interconnect (PCI) host bridges (PHB) provide for DMA transfers, as practiced by the IBM iSeries and pSeries computer platforms, which include a level of address translation called a translation control entry (TCE) table. Systems that require access to system memory beyond 32-bit address implementations employ TCE tables for translating 32-bit DMA addresses into the system's larger physical address space. In particular, existing PCI host bridges employ TCE tables to allow a 32-bit PCI I/O adapter to access system memory beyond the 32-bit address limit. A TCE table may be implemented for each PHB to support all input/output (I/O) adapters on the primary PCI bus or on the secondary PCI buses of any PCI-PCI bridges attached to the primary PCI bus. Each TCE entry may also contain valid bits to control access permission.
TCE tables within logically partitioned platforms are maintained by a firmware component known as the hypervisor, which insures that the data within the TCE table directs the DMA accesses of I/O adapters to the proper target memory. Once the TCE entries are established for the DMA accesses, the hardware will handle the movement of the data between the I/O devices and the system memory. Currently, the hypervisor requires that this target memory is owned by the partition owning the I/O adapter.
DMA address translations may also be “prefetched” in order to improve system performance. For example, in systems with PCI-PCI bridge that provide for PCI prefetch transactions, instead of only reading data from memory for the current DMA request, a data prefetch unit can monitor the DMA address stream requested by the controller and make educated guesses as to the next sequential DMA address likely to be requested in the future. In this manner, the data for the next sequential DMA address should be prefetched and cached into the internal buffer so that the data is ready to be read by the controller (thus avoiding delays or latency that would otherwise occur if the data were not fetched until actually being called for by the controller). Thus, DMA to physical system memory may be prefetched and stored in a cache buffer for quicker system performance.
However, an invalid DMA address translation may be generated on the primary PCI bus by a PCI to PCI bridge for a DMA read transfer initiated by a master PCI agent on the secondary PCI bus due to prefetching. For example, a prefetching action is issued by a PCI-PCI bridge and received at the PHB's TCE logic unit. When the DMA read transfer reaches the end of a page (e.g., 4 KB page), the PCI-PCI bridge's prefetch unit does not know whether or not the next page should be translated. Consequently, the DMA address translation at the PHB's logic unit may be invalid due to cross page boundary prefetching. When a DMA address does not have a valid translation, a sophisticated PHB implementation generates a synchronized exception to the processor to recover the error.
PHBs in some systems, however, do not have this recovery capability. An example of such as system is the JS20 Blade Server, a product of IBM Corporation located in Armonk, N.Y. Upon encountering an invalid DMA address translation, these systems experience a checkstop error, wherein the system becomes unrecoverable. A checkstop error occurs when the system hardware has detected a condition, that it cannot resolve, and which prevents normal operation. While disabling prefetching will remedy the checkstop problem, disabling prefetching will also negatively impact system performance.
Therefore, it would be advantageous to have an improved method, apparatus, and computer instructions for providing valid translation entries in the TCE table for all supported DMA addresses to prevent the occurrence of system errors due to prefetching.